Design of novel 3T ternary DRAM with single word-line using CNTFET

Ternary logic system is the most promising and pursued alternative to prevailing binary systems due energy efficiency of circuits following reduced circuit complexity chip area. In this paper, we have proposed a ternary 3-Transistor Dynamic Random-Access Memory (3 T-DRAM) cell using single word-line for both read write operations. For simulation circuit, used Carbon-Nano-Tube Field Effect Transistor (CNTFET). Here, analyzed operation considering different process variations showed results delay, sensing time, consumed current. Along with basic DRAM design, sense circuitry proper DRAM. The analysis are executed H-SPICE tool Stanford University CNTFET model.